? semiconductor components industries, llc, 2013 august, 2013 ? rev. 1 1 publication order number: nb3l853141/d nb3l853141 2.5v/3.3v 1:5 lvpecl fanout buffer description the nb3l853141 is a low skew 1:5 lvpecl clock fanout buffer designed explicitly for low output skew applications. the nb3l853141 features a multiplexed input which can be driven by either a differential or single ? ended input to allow for the distribution of a lower speed clock along with the high speed system clock. the sel pin will select the differential clock inputs, clk0 & clk0 , when low (or left open and pulled low by the internal pull ? down resistor). when sel is high, the single ? ended clk1 input is selected. the common enable (en ) is synchronous so that the outputs will only be enabled/disabled when they are already in the low state. this avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. the internal flip flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. features ? 700 mhz maximum clock output frequency ? clk0 and clk0 can accept differential lvpecl, lvds, hcsl, lvhstl, sstl, lvcmos ? clk1 can accept lvcmos and lvttl ? five differential lvpecl clock outputs ? 1.5 ns maximum propagation delay ? operating range: v cc = 2.375 v to 3.8 v ? lvcmos compatible control inputs ? selectable differential or lvcmos clock inputs ? synchronous clock enable ? 30 ps max. skew between outputs ? ? 40 c to +85 c ambient operating temperature range ? tssop ? 20 package ? these are pb ? free devices applications ? computing and telecom ? routers, servers and switches ? backplanes marking diagram a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package see detailed ordering and shipping information on page 8 of this data sheet. ordering information http://onsemi.com http://onsemi.com tssop ? 20 dt suffix case 948e nb3l 853141 alyw + figure 1. simplified logic diagram of nb3l853141 q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 clk0 clk0 clk1 sel en 0 1 d q
nb3l853141 http://onsemi.com 2 6 q1 q2 q3 q4 17 18 16 15 14 13 12 4 3578 9 v cc 11 10 q4 q3 q2 q1 nc clk1 clk0 clk 0 nc sel v ee q0 19 20 2 1 v cc q0 en note: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. figure 1. pinout (top view) and logic diagram table 1. function table clk0 clk1 sel en q l h x x x x x l h x l l h h x l l l l h l h l h l* *on next negative transition of clk0 or clk1 x = don?t care table 2. pin description pin number name i/o open default description 1 q0 lvpecl output non ? inverted differential clock output 2 q0 lvpecl output inverted differential clock output 3 q1 lvpecl output non ? inverted differential clock output 4 q1 lvpecl output inverted differential clock output 5 q2 lvpecl output non ? inverted differential clock output 6 q2 lvpecl output inverted differential clock output 7 q3 lvpecl output non ? inverted differential clock output 8 q3 lvpecl output inverted differential clock output 9 q4 lvpecl output non ? inverted differential clock output 10 q4 lvpecl output inverted differential clock output 11 vee power negative supply voltage 12 sel lvcmos / lvttl input low clock select input. when high, selects clk1 input. when low, selects clk0, clk0 inputs. internal pull ? down resistor. 13 nc no connect 14 clk0 multi ? level input high inverted differential clock input. internal pull ? up resistor. 15 clk 0 multi ? level input low non ? inverted differential clock input. internal pull ? down resistor. 16 clk1 lvcmos/lvttl input low single ? ended clock input. internal pull ? down resistor. 17 nc no connect 18 vcc power positive supply voltage 19 en lvcmos/lvttl input low synchronous clock enable input. when low, outputs are enabled. when high, outputs are disabled low. internal pull ? down resistor. 20 vcc power positive supply voltage all vcc and vee pins must be externally connected to a power supply to guarantee proper operation. bypass each supply pin with 0.01 f to gnd.
nb3l853141 http://onsemi.com 3 table 3. attributes (note 1) characteristics value esd protection human body model machine model > 2 kv > 200 v r pu ? pull ? up resistor 50 k r pd ? pull ? down resistor 50 k moisture sensitivity (note 1) tssop ? 20 level 1 flammability rating oxygen index: 28 to 34 ul*94 code v*0 @ 0.125 in transistor count 300 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc lvpecl mode power supply v ee = 0 v 4.6 v v i lvpecl mode input voltage v ee = 0 v v i v cc ? 0.5 to v cc + 0.5 v i out output current continuous surge 50 100 ma ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm tssop ? 20 tssop ? 20 140 50 c/w jc thermal resistance (junction ? to ? case) standard board tssop ? 20 23 to 41 c/w t sol wave solder <2 to 3 sec @ 260 c 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
nb3l853141 http://onsemi.com 4 table 5. dc characteristics v cc = 2.375 v to 3.8 v; v ee = 0 v (note 2); t a = ? 40 c to +85 c symbol characteristic min typ max unit power supply v cc power supply voltage 2.375 3.8 v i ee power supply current (outputs open) 40 55 ma lvpecl outputs (note 3) v oh output high voltage v cc ? 1.4 v cc ? 0.9 v v ol output low voltage v cc ? 2.0 v cc ? 1.7 v v swing output voltage swing, peak ? to ? peak 0.6 1.0 v differential inputs driven single ? ended (note 4) (figures 3 and 4) v ih single ? ended input high voltage 0.5 v cc +0.3 v v il single ? ended input low voltage ? 0.3 v cc ? 1.0 v v th input threshold reference voltage range (note 5) 0.35 v cc ? 0.85 v v ise single ? ended input voltage (v ih ? v il ) 0.3 v cc v differential inputs driven differentially (see figures 5 and 6) (note 6) v ihd differential input high voltage 0.5 v cc ? 0.85 mv v ild differential input low voltage 0 v ihd ? 150 mv v id differential input voltage (v ihd ? v ild ) 0.15 1.3 v v cmr common mode input voltage; (note 7) 0.5 v cc ?0.85 i ih input high current v cc = v in = 3.8 v clk0 clk0 150 5 a i il input low current v cc = 3.8v, v in = 0 v clk0 clk0 ? 5 ? 150 a single ? ended inputs (sel, en , clk1) v ih input high voltage sel, en clk1 2.0 2.0 v cc +0.3 v cc +0.3 v v il input low voltage sel, en clk1 ? 0.3 ? 0.3 0.8 v cc x0.35 v i ih input high current vcc = v in = 3.8 v clk1, sel, en 150 a i il clk1, sel, en clk1, sel, en ? 5 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . 3. lvpecl outputs loaded with 50 to v cc ? 2 v for proper operation. 4. v th , v ih , v il , and v ise parameters must be complied with simultaneously. 5. v th is applied to the complementary input when operating in single ? ended mode. 6. v ihd , v ild , v id and v cmr parameters must be complied with simultaneously. 7. the common mode voltage is defined as v ih .
nb3l853141 http://onsemi.com 5 table 6. ac characteristics, v cc = 2.375 v to 3.8 v, t a = ? 40 c to +85 c (note 8) symbol characteristic min typ max unit f max maximum input clock frequency: v outpp 400 mv clk0/clk0 , v inppmin 250 mv clk1 700 300 mhz n phase noise, f c = 155.52 mhz 10 hz 100 hz 1 khz 10 khz 100 khz 1 mhz 10 mhz 20 mhz offset from carrier ? 100.5 ? 128.2 ? 138.6 ? 147.1 ? 149.7 ? 154.2 ? 154.2 ? 154.2 dbc/ hz t plh , t phl propagation delay to differential outputs, @ 50 mhz note 9 note 10 clk0/clk0 to q/q clk1 to q 0.8 0.8 1.0 1.0 1.5 1.5 ns t n additive phase jitter, rms; f c = 155.52 mhz, integration range: 12 khz ? 20 mhz 0.05 ps tsk(o) output ? to ? output skew; (note 11) 30 ps tsk (pp) part ? to ? part skew; (note 12) 150 ps v inpp input voltage swing/sensitivity (differential configuration) (note 14) 150 1300 mv t r /t f output rise and fall times, 20% to 80%, q, q 200 700 ps odc output clock duty cycle clk0/clk 0 , f 700 mhz, v inppmin 250 mv input duty cycle = 50% clk1, f 250mhz 45 45 55 55 % all parameters measured at f max unless noted otherwise. the cycle ? to ? cycle jitter on the input will equal the jitter on the output. the part does not add jitter 8. measured using a v inppmin source, reference duty cycle = 50% duty cycle clock source. all output loading with external 50 to v cc 2 v. 9. measured from the differential input crossing point to the differential output crossing point. 10. measured from v cc /2 input crossing point to the differential output crossing point. 11. defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output dif ferential cross point s. 12. defined as skew between outputs on dif ferent devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. 13. output voltage swing is a single ? ended measurement operating in differential mode. 14. input voltage swing is a single ? ended measurement operating in differential mode.
nb3l853141 http://onsemi.com 6 figure 2. typical phase noise plot at f carrier = 155.52 mhz at an operating voltage of 3.3 v, room temperature nb3l853141 additive phase jitter @ 155.52 mhz vdd = 3.3 v 12 khz to 20 mhz = 40.3 fs (typical) filter = 12 khz ? 20 mhz source rms jitter = 123.13 fs output rms jitter = 129.56 fs rms addititive jitter rms phase jitter of output 2 rms phase jitter of input 2 40.3 fs 129.56 fs 2 123.13 fs 2 output (dut + source) input source 155.52 m source, f_carrier = 155.52 mhz nb3l853141 f_carrier = 155.52 mhz the above phase noise data was captured using agilent e5052a/b. the data displays the input phase noise and output phase noise used to calculate the additive phase jitter at a specified integration range. the rms phase jitter contributed by the device (integrated between 12 khz and 20 mhz) is 40.3 fs. the additive phase jitter performance of the fanout buffer is highly dependent on the phase noise of the input source. to obtain the most accurate additive phase noise measurement, it is vital that the source phase noise be notably lower than that of the dut. if the phase noise of the source is greater than the device under test output, the source noise will dominate the additive phase jitter calculation and lead to an artificially low result for the additive phase noise measurement within the integration range. the figure above is a good example of the nb3l853141 source generator phase noise having a significantly higher floor such that the dut output results in an additive phase jitter of 40.3 fs. rms addititive jitter rms phase jitter of output 2 rms phase jitter of input 2 40.3 fs 129.56 fs 2 123.13 fs 2
nb3l853141 http://onsemi.com 7 figure 3. differential input driven single ? ended figure 4. v th diagram figure 5. differential inputs driven differentially figure 6. differential inputs driven differentially figure 7. vcmr diagram figure 8. ac reference measurement v ihd v ild v id = |v ihd(in) ? v ild(in) | in in in v th in in in in in q q t plh t phl v inpp = v ih (in) ? v il (in) v cc v ee v thmin v thmax v th in v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v ee v cmrmin v cmrmax v cmr in in v ihdmax v ildmax v id = v ihd ? v ild v ihdtyp v ildtyp v ihdmin v ildmin v th v ih v il figure 9. sel to qx timing diagram tpd tpd v cc / 2 v cc / 2 sel qx qx
nb3l853141 http://onsemi.com 8 figure 10. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? NB3L853141DTG tssop ? 20 (pb ? free) 75 units / rail nb3l853141dtr2g tssop ? 20 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb3l853141 http://onsemi.com 9 package dimensions tssop ? 20 case 948e ? 02 issue c dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . 110 11 20 pin 1 ident a b ? t ? 0.100 (0.004) c d g h section n ? n k k1 jj1 n n m f ? w ? seating plane ? v ? ? u ? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
nb3l853141 http://onsemi.com 10 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nb3l853141/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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